TMC2192 datasheet(48/69 Pages) CADEKA

48 / 69 page

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Deﬁnitions (continued)

Closed Caption Register (0x1D)

76543210

CCD2

Reg

Bit

Name

Description

7-0

CCD2

Second Byte of CC Data.

Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if

CCPAR is HIGH

Closed Caption Register (0x1E)

76543210

CCON

CCRTS

CCPAR

CCFLD

CCLINE

Reg

Bit

Name

Description

CCON

Enable CC Data Packet.

Command the CC data generator to send either CC data or a NULL byte

whenever the specified line is transmitted.

CCRTS

Request To Send Data.

This bit is set HIGH by the user when bytes 0x1C and 0x1D have been

loaded with the next two bytes to be sent. When the encoder’s line count

reaches preceding the line specified in bits 4-0 of this register the data will

be transferred from registers 0x1C and 0x1D, and RTS will be RESET

LOW. A new pair of bytes may then be loaded into registers 0x1C and

0x1D. If CCON = 1 and CCRTS = 0 when the CC line is to be sent, NULL

bytes will be sent.

CCPAR

Auto Parity Generation.

When set HIGH, the encoder replaces the MSB of bytes 0x1C and 0x1D

with a calculated ODD parity. When set LOW, the CC processor transmits

the 16 bits exactly as loaded into registers 0x1C and 0x1D.

CCFLD

CC Field Select.

When LOW, CC data is transmitted on the selected line of ODD fields.

When HIGH, it is sent on EVEN fields.

3-0

CCLINE

CC Line Select.

Defines (with an offset) the line on which CC data are transmitted.

Timing Register (0x1F)

76543210

PDCNT

Reg

Bit

Name

Description

7-0

PDCNT

Pixel Data Control Start.

PDCNT determines the number of pixels (PCK’s) from the midpoint of the

falling edge of horizontal sync to the rising edge of PDC on active video

lines.

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