TMC2192 datasheet(64/69 Pages) CADEKA

64 / 69 page

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Layout Considerations

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Wire-wrap is

not an option. Overall system performance is strongly inﬂu-

enced by the board layout. Capacitive coupling from digital

to analog circuits may result in poor picture quality. Con-

sider the following suggestions when doing the layout:

•

Keep analog traces (CBYPx, VREF, RREF, DACx) as

short and far from all digital signals as possible. The

TMC2192 should be located near the board edge, close

to the analog output connectors.

•

The power plane for the TMC2192 should be separate

from that which supplies other digital circuitry. A single

power plane should be used for all of the VDD pins. If

the power supply for the TMC2192 is the same for the

system's digital circuitry, power to the TMC2192 should

be ﬁltered with ferrite beads and 0.1

µF capacitors to

reduce noise.

•

The ground plane should be solid, not cross-hatched.

Connections to the ground plane should be very short.

•

Decoupling capacitors should be applied liberally to

pins. For best results, use 0.1

µF capacitors. Lead lengths

should be minimized. Ceramic chip capacitors are the

best choice.

•

If there is dedicated digital power plane, it should not

overlap the TMC2192 footprint, the voltage reference,

or the analog outputs. Capacitive coupling of digital

power supply noise from this layer to the TMC2192 and

its related analog circuitry can have an adverse effect on

performance.

•

The PXCK should be handled carefully. Jitter and noise

on this clock or its ground reference will translate to

noise on the video outputs. Terminate the clock line

carefully to eliminate overshoot and ringing.

•

Connect all unused inputs to the TMC2192 to either

ground or VDD. Do not leave them unconnected.

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