поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

TDF8599B датащи(PDF) 10 Page - NXP Semiconductors

номер детали TDF8599B
подробное описание детали  I2C-bus controlled dual channel 43 W/4 W, single channel 85 W/1 W class-D power amplifier with load diagnostics
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDF8599B датащи(HTML) 10 Page - NXP Semiconductors

Back Button TDF8599B Datasheet HTML 6Page - NXP Semiconductors TDF8599B Datasheet HTML 7Page - NXP Semiconductors TDF8599B Datasheet HTML 8Page - NXP Semiconductors TDF8599B Datasheet HTML 9Page - NXP Semiconductors TDF8599B Datasheet HTML 10Page - NXP Semiconductors TDF8599B Datasheet HTML 11Page - NXP Semiconductors TDF8599B Datasheet HTML 12Page - NXP Semiconductors TDF8599B Datasheet HTML 13Page - NXP Semiconductors TDF8599B Datasheet HTML 14Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 54 page
background image
TDF8599B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
10 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
8.3.4 Phase lock operation (Slave mode)
In Slave mode, Phase-Locked Loop (PLL) operation can be used to reduce the jitter effect
of the external oscillator signal connected to pin OSCIO. Phase lock operation is also
needed to enable phase staggering, see Section 8.4.2 on page 13. Phase lock operation
is enabled when the oscillator is in Slave mode by connecting two capacitors (CPLL_s and
CPLL_p) and a resistor (RPLL) between pin SSM and pin AGND (see Figure 8). Connecting
pin SSM to pin AGND disables phase lock operation and causes the slave to directly use
the external oscillator signal. Values for CPLL_s, CPLL_p and RPLL depend on the desired
loop bandwidth (BPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BPLL Ω. The
corresponding values for CPLL_s and CPLL_p are given by Equation 3 and Equation 4:
(3)
Remark: CPLL_p is only needed when 1⁄4 π phase shift is selected. See Section 8.4.2 for
more detailed information.
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BPLL should be 100 × fSSM.
Table 7 lists all oscillator modes.
(1) Only needed when 1
⁄
4 π phase shift is
selected.
a. Off
b. On
Fig 8.
Phase lock operation
Table 7.
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
Oscillator modes
Rosc > 26 kΩ
output
CSSM to pin AGND
master, spread spectrum
Rosc > 26 kΩ
output
shorted to pin AGND
master, no spread spectrum
Rosc =0 Ω
input
CPLL + RPLL to pin AGND
slave, PLL enabled
Rosc =0 Ω
input
shorted to pin AGND
slave, PLL disabled
C
PLL_p
0.032
R
PLL
B
PLL
×
------------------------------- F
[]
=
C
PLL_s
0.8
R
PLL
B
PLL
×
------------------------------- F
[]
=
001aai776
100
µA
SSM
OSCSET
PLL
001aai777
100
µA
PLL
OSCSET
RPLL
CPLL_p(1)
CPLL_s
SSM



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com