TDF8599B datasheet(35/54 Pages) NXP

35 / 54 page

TDF8599B_1

Product data sheet

Rev. 01 — 29 July 2009

35 of 54

NXP Semiconductors

TDF8599B

I2C-bus controlled dual channel class-D power ampliﬁer

14.2 Output power estimation (Parallel mode)

Figure 28 and Figure 29 show the estimated output power at THD = 0.5 % and

THD = 10 % as a function of the supply voltage for different load impedances in parallel

mode.

14.3 Output current limiting

The peak output current is internally limited to 8 A maximum. During normal operation, the

output current should not exceed this threshold level otherwise the output signal will be

distorted. The peak output current can be estimated using Equation 6:

(6)

• Io = output current (A)

• VP = supply voltage (V)

• RL = load impedance (Ω)

• RDSon = on-resistance of power switch (Ω)

• Rs = series resistance of output inductor (Ω)

Example: A 2

Ω speaker can be used with a supply voltage of 19 V before current limiting

is triggered.

Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage

clipping. In Parallel mode, the output current is internally limited above 16 A.

THD = 0.5 %.

RDSon = 0.1 Ω (at Tj = 100 °C), Rs = 0.025 Ω,

tw(min) = 190 ns and IO(ocp) = 16 A (minimum).

(1) RL =1 Ω.

(2) RL =2 Ω.

(3) RL =4 Ω.

THD = 10 %.

RDSon = 0.1 Ω (at Tj = 100 °C), Rs = 0.025 Ω,

tw(min) = 190 ns and IO(ocp) = 16 A (minimum).

(1) RL =1 Ω.

(2) RL =2 Ω.

(3) RL =4 Ω.

Fig 28. Po as a function of VP in parallel mode with

THD = 0.5 %

Fig 29. Po as a function of VP parallel mode with

THD = 10 %

VP (V)

824

(1)

(2)

001aak227

120

150

(W)

(3)

VP (V)

824

(1)

(3)

001aak228

120

180

150

(W)

(2)

DSon

()

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