TMS320F243FN datasheet(12/116 Pages) TI

12 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

TEST SIGNALS (CONTINUED)

TRST

JTAG test reset with internal pulldown. TRST, when driven high, gives

the scan system control of the operations of the device. If this signal is

not connected or driven low, the device operates in its functional mode,

and the test reset signals are ignored.

EMU0

I/O

Emulator I/O pin 0 with internal pullup. When TRST is driven high, this

pin is used as an interrupt to or from the emulator system and is defined

as input/output through the JTAG scan.

EMU1/OFF

I/O

Emulator I/O pin 1 with internal pullup. When TRST is driven high, this

pin is used as an interrupt to or from the emulator system and is defined

as input/output through JTAG scan.

SUPPLY SIGNALS

VSSO

–

Digital logic and buffer ground reference

108

111

117

124

129

131

VDDO

Digital logic and buffer supply voltage

VDDO

–

Digital logic and buffer supply voltage

106

109

VDD

–

Digital logic supply voltage

125

VSS

Digital logic ground reference

VSS

–

Digital logic ground reference

127

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶ Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS

is enabled.

NOTE:

Bold, italicized pin names indicate pin function after reset.

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