TMS320F243FN datasheet(8/116 Pages) TI

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TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS

SPISIMO/

IOPC2

I/O

SPI slave in, master out or GPIO

SPISOMI/

IOPC3

I/O

SPI slave out, master in or GPIO

SPICLK/

IOPC4

I/O

SPI clock or GPIO

SPISTE/

IOPC5

I/O

SPI slave transmit enable (optional) or GPIO

SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS

SCITXD/

IOPA0

I/O

SCI asynchronous serial port transmit data or GPIO

SCIRXD/

IOPA1

I/O

SCI asynchronous serial port receive data or GPIO

CONTROLLER AREA NETWORK (CAN)

CANTX/

IOPC6

115

I/O

CAN transmit data or GPIO

CANRX/

IOPC7

113

I/O

CAN receive data or GPIO

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS

I/O

Device reset. RS causes the ’F243/241 to terminate execution and sets

PC = 0. When RS is brought to a high level, execution begins at location

zero of program memory. RS affects (or sets to zero) various registers

and status bits. When the watchdog timer overflows, it initiates a system

reset pulse that is reflected on the RS pin. This pulse is eight clock cycles

wide.

NMI§

Nonmaskable interrupt. When NMI is activated, the device is interrupted

regardless of the state of the INTM bit of the status register. NMI is

(falling) edge- and low-level-sensitive. To be recognized by the core, this

pin must be kept low for at least one clock cycle after the falling edge.

XINT1/

IOPA2

I/O

External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-

sensitive. To be recognized by the core, these pins must be kept

high/low for at least one clock cycle after the edge. The edge polarity is

programmable.

XINT2/ADCSOC/

IOPD1

I/O

External user interrupt 2. External “start-of-conversion” input for

ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be

recognized by the core, these pins must be kept high/low for at least one

clock cycle after the edge. The edge polarity is programmable.

MP/MC

Microprocessor/Microcomputer mode select. If this pin is low during

reset, the device is put in microcomputer mode and program execution

begins at 0000h of internal program memory (flash EEPROM). A high

value during reset puts the device in microprocessor mode and program

execution begins at 0000h of external program memory.

READY

READY is pulled low to add wait states for external accesses. READY

indicates that an external device is prepared for a bus transaction to be

completed. If the device is not ready, it pulls the READY pin low. The

processor waits one cycle and checks READY again. Note that the

processor performs READY-detection if at least one software wait state

is programmed. To meet the external READY timings, the wait-state

generator control register (WSGR) should be programmed for at least

one wait state.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶ Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS

is enabled.

NOTE:

Bold, italicized pin names indicate pin function after reset.

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