TMS320F243FN datasheet(46/116 Pages) TI

46 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface (’F243 only) (continued)

Wait states can be generated when accessing slower external resources. The wait states operate on

machine-cycle boundaries and are initiated either by using the READY pin or using the software wait-state

generator. READY pin can be used to generate any number of wait states. When using the READY pin to

communicate with slower devices, the ’F243 processor waits until the slower device completes its function and

signals the processor by way of the READY line. Once a ready indication is provided back to the ’F243 from

the external device, execution continues. For external wait states using the READY pin, the on-chip wait-state

generator must be programmed to generate at least one wait state.

wait-state generation (’F243 only)

Wait-state generation is incorporated in the ’F243 without any external hardware for interfacing the ’F243 with

slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external

memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O

port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states

operate on CLKOUT cycle boundaries.

To avoid bus conflicts, writes from the ’F243 always take at least two CLKOUT cycles. The ’F243 offers two

options for generating wait states:

D READYSignal. With the READY signal, you can externally generate any number of wait states. The READY

pin has no effect on accesses to

internal memory.

D On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states.

generating wait states with the READY signal

When the READY signal is low, the ’F243 waits one CLKOUT cycle and then checks READY again. The ’F243

will not continue executing until the READY signal is driven high; therefore, if the READY signal is not used, it

should be pulled high.

The READY pin can be used to generate any number of wait states. However, when the ’F243 operates at full

speed, it may not respond fast enough to provide a READY-based wait state for the first cycle. For extended

wait states using external READY logic, the on-chip wait-state generator should be programmed to generate

at least one wait state.

generating wait states with the ’F243 on-chip software wait-state generator

The software wait-state generator can be programmed to generate zero to seven wait states for a given off-chip

memory space (program, data, or I/O), regardless of the state of the READY signal. These zero to seven wait

states are controlled by the wait-state generator register (WSGR) (I/O FFFFh). For more detailed information

on the WSGR and associated bit functions, refer to the

TMS320C241/C242/C243 DSP Controllers CPU,

System, Instructio2n Set, and Peripherals Reference Guide (literature number SPRU276).

TMS320F243FN датащи(PDF) 46 Page - Texas Instruments