TMS320F243FN datasheet(78/116 Pages) TI

78 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external reference crystal/clock with PLL circuit enabled

The internal oscillator is enabled by connecting a crystal across XTAL1/CLKIN and XTAL2 pins as shown in

Figure 20a. The crystal should be in fundamental operation and parallel resonant, with an effective series

resistance of 30

W and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF.

timings with the PLL circuit enabled

PARAMETER

MIN

TYP

MAX

UNIT

Input clock frequency

Oscillator

MHz

Input clock frequency

CLKIN

MHz

C1, C2

Load capacitance

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 21)

PARAMETER

CLOCK MODE

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–3

H+3

tw(COH)

Pulse duration, CLKOUT high

H–3

H+3

Transition time, PLL synchronized after PLL enabled

before PLL lock,

CLKIN multiply by 4

2500tc(Cl)

timing requirements (see Figure 21)

EXTERNAL REFERENCE

CRYSTAL

MIN

MAX

UNIT

tc(Cl)

Cycle time, XTAL1/CLKIN

5 MHz

200

tf(Cl)

Fall time, XTAL1/CLKIN

tr(Cl)

Rise time, XTAL1/CLKIN

tw(CIL)

Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)

tw(CIH)

Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)

XTAL1/CLKIN

CLKOUT

tc(CI)

tw(CIL)

tw(CIH)

tw(COL)

tw(COH)

tc(CO)

tf(Cl)

tr(Cl)

tr(CO)

tf(CO)

Figure 21. CLKIN-to-CLKOUT Timing for PLL Oscillator Mode, Multiply-by-4 Option with 5-MHz Clock

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