TMS320F243 datasheet(15/116 Pages) TI

15 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F241 PG and FN Packages (Continued)

NAME

QFP

PLCC

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS

SPISIMO/

IOPC2

I/O

SPI slave in, master out or GPIO

SPISOMI/

IOPC3

I/O

SPI slave out, master in or GPIO

SPICLK/

IOPC4

I/O

SPI clock or GPIO

SPISTE/

IOPC5

I/O

SPI slave transmit enable (optional) or GPIO

SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS

SCITXD/

IOPA0

I/O

SCI asynchronous serial port transmit data or GPIO

SCIRXD/

IOPA1

I/O

SCI asynchronous serial port receive data or GPIO

CONTROLLER AREA NETWORK (CAN)

CANTX/

IOPC6

I/O

CAN transmit data or GPIO

CANRX/

IOPC7

I/O

CAN receive data or GPIO

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS

I/O

Device reset. RS causes the ’F243/241 to terminate execution and sets

PC = 0. When RS is brought to a high level, execution begins at location

zero of program memory. RS affects (or sets to zero) various registers

and status bits. When the watchdog timer overflows, it initiates a system

reset pulse that is reflected on the RS pin. This pulse is eight clock cycles

wide.

NMI§

Nonmaskable interrupt. When NMI is activated, the device is interrupted

regardless of the state of the INTM bit of the status register. NMI is

(falling) edge- and low-level-sensitive. To be recognized by the core, this

pin must be kept low for at least one clock cycle after the falling edge.

XINT1/

IOPA2

I/O

External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-

sensitive. To be recognized by the core, these pins must be kept low/high

for at least one clock cycle after the edge. The edge polarity is

programmable.

XINT2/ADCSOC/

IOPD1

I/O

External user interrupt 2. External “start-of-conversion” input for

ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be

recognized by the core, these pins must be kept low/high for at least one

clock cycle after the edge. The edge polarity is programmable.

XF/IOPC0

I/O

O – 1

External flag output (latched software-programmable signal). XF is a

general-purpose output pin. It is set/reset by the SETC XF/CLRC XF

instruction. This pin is configured as an external flag output by all device

resets. It can be used as a GPIO, if not used as XF.

BIO/IOPC1

I/O

Branch control input. BIO is polled by the BCND pma,BIO instruction. If

BIO is low, a branch is executed. If BIO is not used, it should be pulled

high. This pin is configured as a branch control input by all device resets.

It can be used as a GPIO, if not used as a branch control input.

PMT

Enables parallel module test (PMT). Do not connect, reserved for test.

CLOCK SIGNALS

XTAL1/CLKIN

PLL oscillator input pin. Crystal input to PLL/clock source input to PLL.

XTAL1/CLKIN is tied to one side of a reference crystal.

XTAL2

Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a

reference crystal. This pin goes in the high-impedance state when

EMU1/OFF is active low.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

NOTE:

Bold, italicized pin names indicate pin function after reset.

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