TMS320F243 datasheet(39/116 Pages) TI

39 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

’24x legend for the internal hardware (continued)

Table 13. Legend for the ’24x Internal Hardware (Continued)

SYMBOL

NAME

DESCRIPTION

PREG

Product Register

32-bit register holds results of 16

× 16 multiply

PSCALE

Product-Scaling

Shifter

0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the

additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down

the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the

32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle

overhead.

STACK

Stack

STACK is a block of memory used for storing return addresses for subroutines and interrupt-service

routines, or for storing data. The ’C24x stack is 16-bit wide and eight-level deep.

TREG

Temporary

16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count

for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.

’F243/’F241 DSP core CPU

The TMS320x24x devices use an advanced Harvard-type architecture that maximizes processing power by

maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple

bus structure allows data and instructions to be read simultaneously. Instructions support data transfers

between program memory and data memory. This architecture permits coefficients that are stored in program

memory to be read in RAM, thereby eliminating the need for a separate coefficient ROM. This, coupled with a

four-deep pipeline, allows the ’F243/’F241 devices to execute most instructions in a single cycle.

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can

be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved

and restored for subroutines.

The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)

instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST

instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC

instructions. Figure 9 shows the organization of status registers ST0 and ST1, indicating all status bits contained

in each. Several bits in the status registers are reserved and are read as logic 1s. Table 14 lists status register

field definitions.

ST0

ARP

OVM

INTM

ST1

ARB

CNF

SXM

Figure 9. Status and Control Register Organization

Table 14. Status Register Field Definitions

FIELD

FUNCTION

ARB

Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST

instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.

ARP

Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value

is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the

LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.

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