TMS320F243 datasheet(42/116 Pages) TI

42 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

multiplier (continued)

The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision

arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed

data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits

to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The

SQRA (square / add) and SQRS (square / subtract) instructions pass the same value to both inputs of the

multiplier for squaring a data memory value.

After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register

(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store

product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data

bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This

is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot

be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product

half, then, is loaded using the LPH instruction.

central arithmetic logic unit

The TMS320x24x central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical

functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate

it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).

Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional

operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming

from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.

The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or

derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform

Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the

CALU is always provided from the accumulator, and the other input can be provided from the product register

(PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the

ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.

The TMS320x24x devices support floating-point operations for applications requiring a large dynamic range.

The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator

by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the

LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These

instructions are useful in floating-point arithmetic where a number needs to be denormalized — that is,

floating-point to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC)

going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based

on the value contained in the four LSBs of TREG.

The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When

the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator

is loaded with either the most positive or the most negative value representable in the accumulator, depending

on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or

080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the

overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result

in overflow.)

The CALU can execute a variety of branch instructions that depend on the status of the CALU and the

accumulator. These instructions can be executed conditionally based on any meaningful combination of these

status bits. For overflow management, these conditions include the OV (branch on overflow) and EQ (branch

on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides

the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and

BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.

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