TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

32

POST OFFICE BOX 1443

CLKIN

H1

H3

50

51

54

57

58.1

60

59

53

52

55

RESET†‡

IACK

D§

A§

Control

Signals ¶

Asynchronous

Reset Signals #

56

58.2

R/W

10 H1 Clock Cycles

† RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown

occurs; otherwise, an additional delay of one clock cycle can occur.

‡ The R / W output is placed in the high-impedance state during reset and can be provided with a resistive pullup, nominally 18 – 22 k

Ω, if undesirable

spurious writes can occur when these outputs go low.

§ In microprocessor mode (MCBL / MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode

(MCBL / MP = 1), the reset vector is fetched two times, with no software wait states.

¶ Control signals include STRBx and IOSTRB.

# Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx .

Figure 26. RESET Timing