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TMS320C32PCM датащи(PDF) 24 Page - Texas Instruments |
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TMS320C32PCM датащи(HTML) 24 Page - Texas Instruments |
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24 / 44 page ![]() TMS320C32 DIGITAL SIGNAL PROCESSOR SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 memory-read-cycle timing using IOSTRB (see Figure 18) NO ’C32 - 40 ’C32 - 50 ’C32 - 60 UNIT NO. MIN MAX MIN MAX MIN MAX UNIT 11.1 td(H3L-IOSL) Delay time, H3 low to IOSTRB low 0† 11 0† 9 0† 8 ns 12.1 td(H3L-IOSH) Delay time, H3 low to IOSTRB high 0† 11 0† 9 0† 8 ns 13.1 td(H1L-RWL) Delay time, H1 low to R / W high 0† 11 0† 9 0† 8 ns 14.1 td(H1L-A) Delay time, H1 low to A valid 0† 11 0† 9 0† 8 ns 15.1 tsu(D)R Setup time, D before H1 high 13 10 9 ns 16.1 th(D)R Hold time, D after H1 high 0 0 0 ns 17.1 tsu(RDY) Setup time, RDY before H1 high 9 8 7 ns 18.1 th(RDY) Hold time, RDY after H1 high 0 0 0 ns 23 td(H1L-RWH) Delay time, H1 low to R / W low 0† 11 0† 9 0† 8 ns † Assured from characterization but not tested H3 H1 R/W A D RDY IOSTRB 11.1 12.1 14.1 15.1 16.1 18.1 17.1 13.1 23† † See Figure 19 and accompanying table. Figure 18. Memory-Read-Cycle Timing Using IOSTRB |
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