EP1C20F datasheet(13/106 Pages) ALTERA

13 / 106 page

Altera Corporation

2–7

May 2008

Preliminary

Logic Elements

functions. Another special packing mode allows the register output to

feed back into the LUT of the same LE so that the register is packed with

its own fan-out LUT. This provides another mechanism for improved

fitting. The LE can also drive out registered and unregistered versions of

the LUT output.

LUT Chain and Register Chain

In addition to the three general routing outputs, the LEs within a LAB

have LUT chain and register chain outputs. LUT chain connections allow

LUTs within the same LAB to cascade together for wide input functions.

together. The register chain output allows a LAB to use LUTs for a single

combinatorial function and the registers to be used for an unrelated shift

LABs while saving local interconnect resources. “MultiTrack

Interconnect” on page 2–12 for more information on LUT chain and

addnsub Signal

The LE's dynamic adder/subtractor feature saves logic resources by

using one set of LEs to implement both an adder and a subtractor. This

feature is controlled by the LAB-wide control signal

addnsub. The

addnsub signal sets the LAB to perform either A + B or A

−B. The LUT

computes addition; subtraction is computed by adding the two's

complement of the intended subtractor. The LAB-wide signal converts to

two's complement by inverting the B bits within the LAB and setting

carry-in = 1 to add one to the least significant bit (LSB). The LSB of an

adder/subtractor must be placed in the first LE of the LAB, where the

LAB-wide

addnsub signal automatically sets the carry-in to 1. The

Quartus II Compiler automatically places and uses the adder/subtractor

feature when using adder/subtractor parameterized functions.

LE Operating Modes

The Cyclone LE can operate in one of the following modes:

■

Normal mode

■

Dynamic arithmetic mode

Each mode uses LE resources differently. In each mode, eight available

inputs to the LE

⎯the four data inputs from the LAB local interconnect,

carry-in0 and carry-in1 from the previous LE, the LAB carry-in

from the previous carry-chain LAB, and the register chain connection

⎯are

directed to different destinations to implement the desired logic function.

LAB-wide signals provide clock, asynchronous clear, asynchronous

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