EP1C20F datasheet(49/106 Pages) ALTERA

номер детали	EP1C20F

подробное описание детали	Cyclone FPGA Family

PDF	106 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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49 / 106 page

Altera Corporation

2–43

May 2008

Preliminary

I/O Structure

The pin's datain signals can drive the logic array. The logic array drives

the control and data signals, providing a flexible routing resource. The

row or column IOE clocks,

io_clk[5..0], provide a dedicated routing

resource for low-skew, high-speed clocks. The global clock network

generates the IOE clocks that feed the row or column I/O regions (see

“Global Clock Network and Phase-Locked Loops” on page 2–29).

Figure 2–30 illustrates the signal paths through the I/O block.

Figure 2–30. Signal Path through the I/O Block

Each IOE contains its own control signal selection for the following

control signals:

oe, ce_in, ce_out, aclr/preset, sclr/preset,

clk_in, and clk_out. Figure 2–31 illustrates the control signal

selection.

Row or Column

io_clk[5..0]

io_datain

comb_io_datain

io_dataout

io_coe

ce_in

ce_out

io_cce_in

aclr/preset

io_cce_out

sclr

io_caclr

clk_in

io_cclk

clk_out

dataout

Data and

Control

Signal

Selection

IOE

To Logic

Array

From Logic

Array

To Other

IOEs

io_csclr

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