LTC4241

11

sn4241 4241f

Timer

During a power-up sequence for the PCI power supplies,

a 22

µA current source is connected to the TIMER pin and

current limit faults are ignored until the voltage ramps to

up a PCI slot that can accommodate boards with a wide

range of capacitive loads on the supplies. The power-up

time for any one of the four outputs will be:

t

CV

II

ON

LOAD

OUT

LIMIT

LOAD

≅









2•

•

–

substituting the variables in the above equation with the

appropriate values, the turn-on time for the other three

outputs can be calculated. The timer period should be set

longer than the maximum supply turn-on time but short

enough to not exceed the maximum safe operating area of

the pass transistor during a short-circuit. The timer period

is given by:

APPLICATIO S I FOR ATIO

The current in each pass transistor increases until it

reaches the current limit for each supply. Each supply is

allowed to power up at the rate dV/dt = 60

µA/C1 or as

determined by the current limit and the load capacitance

on the supply line, whichever is slower. Current limit faults

are ignored while the TIMER pin voltage is ramping up and

voltages are within tolerance, the PWRGD pin will pull low.

Power-Down Sequence for PCI Power Supplies

When the ON pin is pulled low, a power-down sequence

begins for all the PCI power supplies (Figure 3).

Internal switches are connected to each of the output

supply voltage pins to discharge the load capacitors to

ground. The TIMER pin is immediately pulled low and the

internal 12V and –12V switches are turned off. The GATE

pin is pulled to ground by an internal 200

µA current

source. This turns off the external pass transistors in a

controlled manner and prevents the load current on the

3.3V and 5V supplies from going to zero instantaneously

and glitching the power supply voltages. When any of the

output voltages dips below its threshold, the PWRGD pin

pulls high.

Figure 2. Normal Power-Up Sequence

Figure 3. Normal Power-Down Sequence

ON

10V/DIV

TIMER

10V/DIV

GATE

10V/DIV

PWRGD

10V/DIV

5V/DIV

5V/DIV

FAULT

10V/DIV

10ms/DIV

4241 F03

t

CV

A

TIMER

TIMER

=

µ

•.

11 1

22

ON

10V/DIV

TIMER

10V/DIV

GATE

10V/DIV

PWRGD

10V/DIV

5V/DIV

5V/DIV

FAULT

10V/DIV

10ms/DIV

4241 F02