LTC4241IGN datasheet(8/16 Pages) LINER

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LTC4241

sn4241 4241f

PI FU CTIO S

a constant voltage across the sense resistor and a

constant current through the switch. A foldback feature

makes the current limit decrease as the voltage at the

3VOUT pin approaches ground. To disable the current limit,

3VSENSE and 3VIN can be shorted together.

GATE (Pin 15): High Side Gate Drive for the 3.3V and 5V

PCI Supplies External N-channel MOSFETs. Requires an

external series RC network for the current limit loop

compensation and setting the minimum ramp-up rate.

During power-up, the slope of the voltage rise at the GATE

is set by the internal 60

µA pull up current source and the

external GATE capacitor connected to ground. During

power-down, the slope of the falling voltage is set by the

200

µA current source connected to ground and the exter-

nal GATE capacitor.

5VSENSE (Pin 16): 5V Current Limit Set Pin. With a sense

resistor placed in the supply path between 5VIN and

5VSENSE, the GATE pin voltage will be adjusted to maintain

a constant voltage across the sense resistor and a con-

stant current through the switch. A foldback feature makes

the current limit decrease as the voltage at the 5VOUT pin

approaches ground. To disable the current limit, 5VSENSE

and 5VIN can be shorted together.

5VIN (Pin 17): 5V Supply Sense Input. Used to monitor the

5V input supply voltage. An undervoltage lockout circuit

prevents the switches from turning on when the voltage at

the 5VIN pin is less than 3.9V.

5VOUT (Pin 18): 5V Output Monitor. Used to monitor the

5V output supply voltage. The PWRGD signal cannot go

low until the 5VOUT pin exceeds 4.65V.

VEEOUT (Pin 19): –12V Supply Output. A 1.2Ω switch is

connected between VEEIN and VEEOUT. VEEOUT must

fall below –10.5V before the PWRGD signal can go low on

the LTC4241.

12VOUT (Pin 20): 12V Supply Output. A 0.5Ω switch is

connected between 12VIN and 12VOUT. 12VOUT must

exceed 11.1V before the PWRGD signal can go low on the

LTC4241

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