LTC4264IDE datasheet(12/24 Pages) LINER

12 / 24 page

LTC4264

4264f

UNDERVOLTAGE LOCKOUT

The IEEE 802.3af speciﬁcation dictates a maximum turn-

on voltage of 42V and a minimum turn-off voltage of 30V

for the PD. In addition, the PD must maintain large on-off

hysteresis to prevent current-resistance (I-R) drops in the

wiring between the PSE and the PD from causing start-up

oscillation. The LTC4264 incorporates an undervoltage

lockout (UVLO) circuit that monitors line voltage at VIN to

determine when to apply power to the PD load (Figure 7).

Before power is applied to the load, the VOUT pin is high

impedance and there is no charge on capacitor C1. When

the input voltage rises above the UVLO turn-on thresh-

old, the LTC4264 removes the classiﬁcation load current

and turns on the internal power MOSFET. C1 charges up

under LTC4264 inrush current limit control and the VOUT

pin transitions from 0V to VIN as shown in Figure 3. The

LTC4264 includes a hysteretic UVLO circuit on VIN that

keeps power applied to the load until the magnitude of the

input voltage falls below the UVLO turn-off threshold. Once

VIN falls below UVLO turn-off, the internal power MOSFET

disconnects VOUT from VIN and the classiﬁcation current

is re-enabled. C1 will discharge through the PD circuitry

and the VOUT pin will go to a high impedance state.

INPUT CURRENT LIMIT

IEEE 802.3af speciﬁes a maximum inrush current and also

speciﬁes a minimum load capacitor between the GND and

VOUT pins. To control turn-on surge currents in the system

the LTC4264 integrates a dual current limit circuit using an

onboard power MOSFET and sense resistor to provide a

complete inrush control circuit without additional external

components.

At turn-on, the LTC4264 will limit the inrush current to

ILIMIT_LOW,allowingtheloadcapacitortorampuptotheline

voltage in a controlled manner without interference from

the PSE current limit. By keeping the PD current limit below

the PSE current limit, PD power up characteristics are well

controlled and independent of PSE behavior. This ensures

interoperability regardless of PSE output characteristics.

After load capacitor C1 is charged up, the LTC4264 switches

to the high input current limit, ILIMIT_HIGH. This allows the

LTC4264 to deliver up to 35W to the PD load for high power

applications. To maintain compatibility with IEEE 802.3af

power levels, it is necessary for the PD designer to ensure

the PD steady-state power consumption remains below

the limits shown in Table 2. The LTC4264 maintains the

high input current limit until the port voltage drops below

the UVLO turn-off threshold.

APPLICATIONS INFORMATION

GND

µF

MIN

VIN

VOUT

LTC4264

4264 F07

PSE

UNDERVOLTAGE

LOCKOUT

CIRCUIT

LOAD

CURRENT-LIMITED

TURN ON

INPUT

LTC4264

VOLTAGE

POWER MOSFET

0V TO UVLO*

OFF

>UVLO*

*UVLO INCLUDES HYSTERESIS

RISING INPUT THRESHOLD

≅ –38.9V

FALLING INPUT THRESHOLD

≅ –30.6V

Figure 7. LTC4264 Undervoltage Lockout

LTC4264IDE датащи(PDF) 12 Page - Linear Technology

LTC4264IDE датащи(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL