LTC4264IDE datasheet(8/24 Pages) LINER

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LTC4264

4264f

APPLICATIONS INFORMATION

4264 F02

SMAJ58A

0.1

µF

Tx1

Rx1

Tx1

SMAJ58A

VEE

SENSE GATE OUT

VDD

AUTO

CMPD3003

10k

0.1

µF

0.25

Ω

IRLR3410

S1B

1/4

LTC4259A

DGND BYP

AGND

DETECT

3.3V

–54V

RJ45

CAT5

PSE

RCLASS

VIN

PWRGD

VOUT

LTC4264

GND

DF1501S

DC/DC

CONVERTER

µF

MIN

–

VOUT

GND

0.47

µF

SMAJ58A

0.1

µF

Tx2

Rx2

Tx2

VEE

SENSE GATE OUT

CMPD3003

10k

0.25

Ω

IRLR3410

S1B

1/4

LTC4259A

DETECT

–54V

GND

0.47

µF

0.1

µF

SMAJ58A

RCLASS

VIN

PWRGD

VOUT

LTC4264

GND

DC/DC

CONVERTER

µF

MIN

0.1

µF

AGND

Figure 2. 4-Pair High Power PoE Gigabit Ethernet System Diagram

The LTC4264 is speciﬁcally designed to implement the

front end of a high power PD for power-hungry PoE ap-

plications that must operate beyond the power limits of

IEEE 802.3af. LTC4264 uses a precision, dual current limit

that keeps inrush below IEEE 803.2af levels to ensure

interoperability with any PSE. After inrush is complete,

the LTC4264 input current limit switches to the ILIMIT_HIGH

level, using an onboard, 750mA power MOSFET. This al-

lows a PD (supplied by a custom PSE) to deliver power

above the IEEE 802.3af 12.95W maximum, sending up

to 35W to the PD load. The LTC4264 uses established

IEEE 802.3af detection and classiﬁcation methods to

maintain compliance and includes an extended program-

mable Class 5 range for use in custom PoE applications.

The LTC4264 features both active-high and active-low

power good signaling for simpliﬁed interface to any DC/DC

converter. The SHDN pin on the LTC4264 can be used to

provide a seamless interface for external wall adapter or

other auxiliary power options. The ILIM_EN pin provides the

option to remove the high current limit, ILIMIT_HIGH. The

LTC4264 includes an onboard signature resistor, precision

UVLO, thermal overload protection and is available in a

thermally-enhanced 12-lead 4mm

× 3mm DFN package

for superior high current performance.

OPERATION

The LTC4264 high power PD interface controller has sev-

eral modes of operation depending on the applied input

voltage as shown in Figure 3 and summarized in Table 1.

These various modes satisfy the requirements deﬁned

in the IEEE 802.3af speciﬁcation. The input voltage is

applied to the VIN pin with reference to the GND pin and

is always negative.

Table 1. LTC4264 Operational Mode as a Function

of Input Voltage

INPUT VOLTAGE

LTC4264 MODE OF OPERATION

0V to –1.4V

Inactive

–1.5V to –10.1V

25k Signature Resistor Detection

–10.3V to –12.4V

Classiﬁcation Load Current Ramps Up from 0% to

100%

–12.5V to UVLO*

Classiﬁcation Load Current Active

UVLO* to –57V

Power Applied to PD Load

*UVLO includes hysteresis.

Rising input threshold

≅ –38.9V

Falling input threshold

≅ –30.6V

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