3-81

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

Multiple-Slope Conversion Principles

One limitation of the dual-slope measurement tech-

nique is conversion speed. In a typical dual-slope method,

the auto-zero and integrate times are each one-half of the

(65,536) clock pulses are required for auto-zero, integrate,

and deintegrate phases, respectively. The large number of

clock cycles effectively limits the conversion rate to about

2.5 conversions per second, when a typical analog CMOS

fabrication process is used.

The TC850 uses a multiple-slope conversion technique

to increase conversion speed (Figure 2B). This technique

makes use of a two-slope deintegration phase and permits

15-bit resolution up to 40 conversions per second.

During the TC850's deintegration phase, the integration

capacitor is rapidly discharged to yield a resolution of 9 bits.

At this point, some charge will remain on the capacitor. This

remaining charge is then slowly deintegrated, producing an

THEORY OF OPERATION

The TC850 is a multiple-slope, integrating analog-to-

digital converter (ADC). The multiple-slope conversion pro-

cess, combined with chopper-stabilized amplifiers, results

in a significant increase in ADC speed, while maintaining

very high resolution and accuracy.

Dual-Slope Conversion Principles

The conventional dual-slope converter measurement

cycle (shown in Figure 2A) has two distinct phases:

(1) Input signal integration

(2) Reference voltage integration (deintegration)

The input signal being converted is integrated for a fixed

time period, measured by counting clock pulses. An oppo-

site polarity constant reference voltage is then integrated

until the integrator output voltage returns to zero. The

reference integration time is directly proportional to the input

signal.

In a simple dual-slope converter, complete conversion

requires the integrator output to "ramp-up" and "ramp-

down." Most dual-slope converters add a third phase, auto-

zero. During auto-zero, offset voltages of the input buffer,

integrator, and comparator are nulled, thereby eliminating

the need for zero-offset adjustments.

Dual-slope converter accuracy is unrelated to the inte-

grating resistor and capacitor values, as long as they are

stable during a measurement cycle. By converting the

unknown analog input voltage into an easily-measured

function of time, the dual-slope converter reduces the need

for expensive, precision passive components.

Noise immunity is an inherent benefit of the integrating

conversion method. Noise spikes are integrated, or aver-

aged, to zero during the integration period. Integrating ADCs

are immune to the large conversion errors that plague

successive approximation converters in high-noise environ-

ments.

A simple mathematical equation relates the input signal,

reference voltage, and integration time:

Figure 1. Standard Circuit Configuration

BUSY

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CS

CE

WR

RD

CONT/DEMAND

OVR/POL

L/H

16

8

9

10

11

12

13

14

15

1

2

3

4

5

6

7

17

TC850

0.01

µF INPUT

+1.6384V

+0.0265V

100 M

Ω

120 M

Ω

1

1

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

IN

+

IN

–

COMMON

REF1

+

REF2

+

+

REF–

BUFFER

OSC1

OSC2

INTIN

INTOUT

CINTB

CINTA

+

CREF1

–

CREF1

–

CREF2

CREF2

RINT

CINT

CBUFACBUFB

COMP

TEST

NC

18

21

28

27

29

26

19

23

24

25

35

34

37

38

36

33

39

30

31

61.44 kHz

20

22

40

–5V

+5V

DGND

32

**

**

NOTES: Unless otherwise specified, all 0.1

µF capacitors are film dielectric.

Ceramic capacitors are not recommended.

NC = No internal capacitors

*Polypropylene capacitors.

** 100pF Mica capacitors.

∫

0

,

RC

1

RC

TC850

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER