3-79

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

ELECTRICAL CHARACTERISTICS (Cont.)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Low/High Byte Access Time

CS = HIGH, CE = LOW, RD = LOW (Note 1)

—

140

300

nsec

Clock Setup Time

Positive or Negative Pulse Width

100

—

—

nsec

RD Minimum Pulse Width

CS = HIGH, CE = LOW (Note 2)

450

230

—

nsec

RD Minimum Delay Time

CS = HIGH, CE = LOW (Note 2)

150

50

—

nsec

WR Minimum Pulse Width

CS = HIGH, CE = LOW, Demand Mode

75

25

—

nsec

Clock Setup Time

Positive or Negative Pulse Width

100

—

—

nsec

2. Continuous mode, CONT/DEMAND = HIGH. Figure 12 timing diagram.

recommended.

TC850CPL

TC850IJL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

COMMON

CBUFB

BUFFER

INTIN

INTOUT

COMP

NC = NO INTERNAL CONNECTION

GND

CINTA

CBUFA

CINTB

IN

–

IN

+

REF

–

TEST

OSC2

OSC1

BUSY

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

L/H

OVR/POL

CONT/DEMAND

RD

CE

CS

WR

VSS

VDD

REF1

+

REF2

+

CREF1

+

CREF1

–

CREF2

–

CREF2

+

CREF2

COMMON

33

34

35

36

37

38

39

13

10

9

8

7

18

19

20

21

23

24

6

543

1

44

2

22

43

42

41

40

25

26

27

28

32

14

31

15

30

16

29

17

11

12

TC850CLW

TC850ILW

CBUFB

CINTA

CBUFA

CINTB

IN

–

NC

IN

+

DB0

DB1

DB2

DB3

DB4

NC

DB5

DB6

DB7

OVR/POL

L/H

REF2

+

–

CREF2

+

PIN CONFIGURATIONS

TC850

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER