3-89

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

Figure 9. Conversion Timing, Demand Mode

Figure 10. Bus Output Timing, Demand Mode

WR PULSES ARE IGNORED

836 CLOCK CYCLES

1100 CLOCK CYCLES

INTERNAL

CLOCK

BUSY

DB0-DB7

CS

.

CE

NEXT CONVERT

COMMAND WILL

BE RECOGNIZED

PREVIOUS CONVERSION

DATA VALID

DATA MEANINGLESS

NEW CONVERSION DATA VALID

NEXT

CONVERSION

CAN BEGIN

319 CLOCK

CYCLES

125 CLOCK

CYCLES

. . . .

. . . . . . . .

WR

DB0-DB6

DB7

OVR/POL

L/H

tCE

tDHC

tDHR

tRE

CS

.

CE

HI-Z

*

DATA BITS 8 TO 14

HIGH IMPEDANCE

HIGH IMPEDANCE

DONT' CARE

DONT' CARE

DATA BITS

0 T0 6

HI-Z

"1"= INPUT

OVERRANGE

"1"= POSITIVE

POLARITY

DATA BIT 7

tOP

tLH

RD

NOTE: CONT/DEMAND = LOW

*RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a

µP bus interface)

or remain LOW during the entire DATA-READ sequence (i.e.,

µP I/O port interface).

TC850

15-BIT, FAST-INTEGRATING CMOS

ANALOG-TO-DIGITAL CONVERTER