TC820CPL datasheet(20/22 Pages) TELCOM

20 / 22 page

3-168

TELCOM SEMICONDUCTOR, INC.

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

TC820

Figure 22. Window Comparator Logic Probe

acitors added across the input pull-down resistors to stretch

the input pulse and permit viewing short-duration input

pulses.

External Peak Detection

The TC820 will hold the highest A/D conversion or

frequency reading indefinitely when the PK HOLD input is

connected to VDD. However, the analog peak input must be

present during the A/D converter's signal integrate period.

For slowly changing signals, such as temperature, the peak

reading will be properly converted and held.

If rapidly changing analog signals must be held, an

external peak detector should be added. An inexpensive

circuit can be made from an op amp and a few discrete

components, as shown in Figure 23. The droop rate of the

external peak detector should be adjusted so that the held

voltage will not decay below the desired accuracy level

during the converter's 400msec conversion time.

Liquid Crystal Display (LCD)

The TC820 drives a triplex (multiplexed 3:1) LCD with

three backplanes. The LCD can include decimal points,

polarity sign, and annunciators for overrange, peak hold,

high and low logic levels, and low battery. Table IV shows the

assignment of the display segments to the backplanes and

segment drive lines. The backplane drive frequency is

obtained by dividing the oscillator frequency by 240.

Backplane waveforms are shown in Figure 24. These

appear on outputs BP1, BP2, and BP3. They remain the

same regardless of the segments being driven.

Other display output lines have waveforms that vary

VDD

TC820

DP1/HI

LOGIC

DP0/LO

DGND

1N4148

+9V

Ω

LOGIC

PROBE

INPUT

NOTE: Select R1, R2, R3 for desired logic thresholds.

depending on the displays values. Figure 25 shows a set of

waveforms for the a, g, d outputs of one digit for several

combinations of "on" segments.

Figure 23. External Peak Detector

VDD

TC820

VSS

PK HOLD

0.01

µF

OFFSET

NULL

1N4148

+9V

10k

Ω

VIN

TL061

Table IV. LCD Backplane and Segment Assignments

44-Pin

LCD

40-Pin DIP

Flat Pkg

Display

Pin No.

BP1

BP2

BP3

LOW

"—"

DP3

HIGH

DP2

OVER

DP1

PEAK

BATT

2,16*

—

BP3

—

BP2

—

BP1

—

*Connect both pins 2 and 16 of LCD to TC820 BP3 output.

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