TC820CPL datasheet(19/22 Pages) TELCOM

19 / 22 page

3-167

TELCOM SEMICONDUCTOR, INC.

VDD

TC820

LOGIC

PROBE

INPUT

+9V

74HC14

LOGIC

DP1/HI

DP0/LO

DGND

TC820

3-3/4 A/D CONVERTER WITH

FREQUENCY COUNTER

AND LOGIC PROBE

Figure 18. Reference Voltage Connections

Figure 20. Frequency Counter External Buffer

Logic Probe Inputs

The DP0/LO and DP1/HI inputs provide the logic probe

inputs when the LOGIC input is high. Driving either DP0/LO

or DP1/HI to a logic high will turn on the appropriate LCD

annunciator. When DP0/LO is high, the buzzer will be on.

To provide a "single input" logic probe function, external

buffers should be used. A simple circuit is shown in Figure

21. This circuit will turn the appropriate annunciator on for

high and low level inputs.

If carefully controlled logic thresholds are required, a

window comparator can be used. Figure 22 shows a typical

circuit. This circuit will turn on the high or low annunciators

when the logic thresholds are exceeded, but the resistors

connected from DP0/LO and DP1/HI to DGND will turn both

annunciators off when the logic probe is unconnected.

The TC820 logic inputs are not latched internally, so

pulses of short duration will usually be difficult or impossible

to see. To display short pulses properly, the input pulse

should be "stretched." The circuit of Figure 22 shows cap-

Figure 21. Simple External Logic Probe Buffer

applied to the reference input. If the unknown equals the

standard, the input voltage will equal the reference voltage

and the display will read 2000. The displayed reading can be

determined from the following expression:

Displayed reading =

2000

The display will overrange for values of RUNKNOWN ≥ 2

RSTANDARD.

Buffering the FREQ Input

When the FREQ/VOLTS input is high and the LOGIC

input is low, the TC820 will count pulses at the RANGE/

FREQ input. The time base will be fOSC/40,000, or 1 second

with a 40kHz clock. The signal to be measured should swing

from VDD to DGND. The RANGE/FREQ input has CMOS

input levels without hysteresis. For best results, especially

with low-frequency sine-wave inputs, an external buffer with

hysteresis should be added. A typical circuit is shown in

Figure 20.

Figure 19. Low Parts Count Ratiometric Resistance Measurement

TC820

22k

Ω

VDD

VSS

REF

–

REF

ANALOG

COMMON

SET V

= 1/2 V

REF

FULL SCALE

(a) Internal Reference

(b) External Reference

REF

–

REF

COMMON

TC04A

1.2V

REF

Ω

REF

Ω

TC820

DGND

FREQUENCY

INPUT

GND

DGND

74HC14

RANGE/FREQ

FREQ/VOLTS

VDD

µF

+9V

RUNKNOWN

RSTANDARD

TC820

RSTANDARD

RUNKNOWN

ANALOG

COMMON

VDD

REF

–

REF

–

LCD

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