6

6396A–DRMSD–15-Oct-08

ATSAM2533

DBCLK

85

IN 5VT

Debug clock, should be connected to VD33 under normal operation. If DBCLK is found low

just after RESET, then the internal ROM debugger/Flash programmer is started

DBDATA

87

I/O 5VT

Debug data, allows serial communication for debug/Flash programming. This pin has a built-

in pull down.

DBACK

86

OUT

Debug ack, toggled each time a bit is received/sent on DBDATA

MIDI IN

96

IN 5VT

MIDI IN, input. This pin has a built-in pull up.

MIDI OUT

94

OUT

MIDI OUT, output.

WA0-23

35-40,

43-48,

55-58,

60-67

OUT

External memory address (ROM/Flash). Up to 32 Mega bytes.

WD0-15

14-24,

27-31

I/O 5VT

External ROM/Flash data.

WCS

70

OUT

External ROM/Flash chip select, active low.

WWE

72

OUT

External Flash write enable, active low.

WOE

71

OUT

External ROM/Flash output enable, active low.

TEST0-1

95, 78

IN

Test pins, should be returned to GND.

PDWN

32

IN

Power down, active low. When power down is active, WCS, WWE, WOE, address and data

lines are floated. All other outputs are set to 0. The crystal oscillator is stopped, OUTVC18 is

set to 0 and 1.8V supply voltage is removed from the core. To exit from power down, PDWN

must be set to VD33, then RESET applied. When unused this pin must be connected to

VD33.

NC

73, 74

–

Not connected pins.

Table 5-1.

ATSAM2523 Pinout by Name (Continued)

Name

Pin#

TYPE

Function