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6396A–DRMSD–15-Oct-08

ATSAM2533

3.

Functional Description

3.1

Synthesis/DSP Engine

The synthesis/DSP engine operates on a frame timing basis with the frame subdivided into 64

processes slots. Each process is itself divided into 16 micro-instructions known as an “algorithm”

Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the

device to be programmed for a number of audio signal generation/processing applications. The

synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as

wavetable synthesis with interpolation, alternate loop and 24dB resonant filtering for each voice.

Slots may be linked together (ML RAM) to allow implementation of more complex synthesis

algorithms.

A typical application will use half the capacity of the synthesis/DSP engine for synthesis, thus

providing state of the art 32-voice wavetable polyphony. The remaining processing power will be

used for typical functions like reverberation, chorus, audio in processing, surround effect, equal-

izer, etc.

Frequently accessed synthesis/DSP parameter data are stored into 5 banks of on-chip RAM

memory. Sample data or delay lines, which are accessed relatively infrequently are stored in

external ROM or internal 32K x16 RAM memory. The combination of localized micro-program

memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS).

Separate busses from each of the on-chip parameter RAM memory banks allow highly parallel

data movement to increase the effectiveness of each micro-instruction. With this architecture, a

single micro-instruction can accomplish up to 6 simultaneous operations (add, multiply, load,

store, etc.), providing a potential throughput of 300 million operations per second (MOPS).

3.2

Enhanced P16 Control Processor and I/O Functions

The Enhanced P16 control processor is the new version of P16 processor with added instruc-

tions allowing C compiling. The P16 control processor is a general purpose 16-bit CISC

processor core, which runs from external memory. It includes 256 words of local RAM data

memory.

The P16 control processor writes to the parameter RAM blocks within the synthesis/DSP core in

order to control the synthesis process. In a typical application, the P16 control processor parses

and interprets incoming commands from the MIDI UART or from the parallel 8-bit interface and

then controls the Synthesis/DSP by writing into the parameter RAM banks in the DSP core.

Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control proces-

sor by periodically updating the DSP parameter RAM variables.

The P16 control processor interfaces with other peripheral devices, such as the system control

and status registers, the on-chip MIDI UART, the on-chip timers and the parallel 8-bit interface

through specialized “intelligent” peripheral I/O logic. This I/O logic automates many of the sys-

tem I/O transfers to minimize the amount of overhead processing required from the P16.

The parallel 8-bit interface is implemented using one address lines (A0), a chip select signal,

read and write strobes from the host and an 8-bit data bus (D0-D7).

Karaoke and keyboard applications can take advantage of the parallel 8-bit interface to commu-

nicate with the ATSAM2533 at high speed, with the MIDI IN and MIDI OUT signals remaining

available.