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6396A–DRMSD–15-Oct-08

ATSAM2533

12. Recommended Board Layout

Like all HCMOS high integration ICs, following simple rules of board layout are mandatory for

reliable operation:

• GND, VD33, VD18 distribution, decouplings

All GND, VD33, VD18 pins should be connected. A GND plane is strongly recommended below

the ATSAM2533. The board GND + VD33 planes could be in grid form to minimize EMI.

Recommended VD18 decoupling is 0.1 µF close to the VD18 pin and 470 pF in parallel with 2.2

or 4.7 µF close to OUTVC18 pin. VD33 requires 0.1 uF at each corner of the IC with an addi-

tional 10 µFT capacitor that should be placed close to the crystal.

• Crystal, LFT

The paths between the crystal, the crystal compensation capacitors and the ATSAM2533 should

be short and shielded. The ground return from the compensation capacitors should be the GND

plane from ATSAM2533.

• Busses

Parallel layout from D0-D7 and WA0-WA23/WD0-WD15 should be avoided. The D0-D7 bus is

an asynchronous type bus. Even on short distances, it can induce pulses on WA0-WA23/WD0-

WD15 which can corrupt address and/or data on these busses.

A ground plane should be implemented below the D0-D7 bus, which is connected to the host

and to the ATSAM2533 GND.

A ground plane should be implemented below the WA0-WA23/WD0-WD15 bus, which is con-

nected to the ROM/Flash grounds and to the ATSAM2533.

• Analog section

A specific AGND ground plane should be provided, which is connected to the GND ground by a

single trace. No digital signals should cross the AGND plane.

Refer to the CODEC vendor recommended layout for correct implementation of the analog

section.