12

6396A–DRMSD–15-Oct-08

ATSAM2533

Figure 9-2.

Host Interface Write Cycle

9.2.2

IO Status Register

Status register is read when A0 = 1, RD = 0, CS = 0.

• TE: Transmit Empty

If 0, data from ATSAM2533 to host is pending and IRQ is high. Reading the data at A0 = 0 will set TE to 1 and clear IRQ.

• RF: Receiver Full

If 0, then ATSAM2533 is ready to accept DATA from host.

A0

CS/

WR/

D0-D7

tavcs

tcslwrl

tpwr

twrhcsh

tdws

tdwh

twrcyc

Table 9-2.

Timing Parameters

Symbol

Parameter

Min

Typ

Mx

Unit

tavcs

Address valid to chip select low

0

-

-

ns

tcslrdl

Chip select low to RD low

5

-

-

ns

trdhcsh

RD high to CS high

5

-

-

ns

tprd

RD pulse width

50

-

-

ns

trdldv

Data out valid from RD

-

-

20

ns

tdrh

Data out hold from RD

5

-

10

ns

tcslrwrl

Chip select low to WR low

5

-

-

ns

twrhcsh

WR high to CS high

5

-

-

ns

tpwr

WR pulse width

50

-

-

ns

tdws

Write data setup time

10

-

-

ns

tdwh

Write data hold time

0

-

-

ns

twrcyc

Write cycle

128

-

-

tck

76543210

TE

RF

XXXXXX