EP910 datasheet(41/42 Pages) ALTERA

номер детали	EP910

подробное описание детали	The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology

PDF	42 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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Altera Corporation

785

Classic EPLD Family Data Sheet

Notes to tables:

(1)

These values are specified in Table 24 on page 781.

(2)

The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.

(3)

Measured with a device programmed as four 12-bit counters.

(4)

Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter

applies for both global and array clocking.

(5)

The fMAX values represent the highest frequency for pipelined data.

(6)

Sample-tested only for an output change of 500 mV.

Pin-Out

Information

Table 32 provides pin-out information for EP1810 devices in 68-pin PGA

packages.

Table 32. EP1810 PGA Pin-Outs

Function

I/O

F10

GND

INPUT

I/O

B10

I/O

F11

I/O

INPUT

I/O

B11

I/O

VCC

INPUT

I/O

INPUT

CLK4

/INPUT

I/O

G10

I/O

INPUT

CLK3

/INPUT

C10

I/O

G11

I/O

INPUT

C11

I/O

K10

I/O

K11

I/O

A10

I/O

H10

I/O

D10

I/O

H11

I/O

D11

I/O

INPUT

I/O

CLK1

/INPUT

INPUT

I/O

J10

I/O

CLK2

/INPUT

INPUT

E10

I/O

J11

I/O

INPUT

VCC

E11

I/O

INPUT

I/O

INPUT

GND

I/O

L10

I/O

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