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EP910 датащи(PDF) 28 Page - Altera Corporation

номер детали EP910
подробное описание детали  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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производитель  ALTERA [Altera Corporation]
домашняя страница  http://www.altera.com
Logo ALTERA - Altera Corporation

EP910 датащи(HTML) 28 Page - Altera Corporation

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Altera Corporation
Classic EPLD Family Data Sheet
Tables 19 and 20 show the timing parameters for EP910 devices.
Table 19. EP910 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
EP910-30
EP910-35
EP910-40
Non-
Turbo
Adder (3)
Unit
Min Max Min Max Min Max
tPD1
Input to non-registered output
C1 = 35 pF
30.0
35.0
40.0
30.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
33.0
38.0
43.0
30.0
ns
tPZX
Input to output enable
C1 = 35 pF
30.0
35.0
40.0
30.0
ns
tPXZ
Input to output disable
C1 = 5 pF
(4)
30.0
35.0
40.0
30.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
33.0
38.0
43.0
30.0
ns
fMAX
Maximum frequency
(5)
41.7
37.0
32.3
0.0
MHz
tSU
Global clock input setup time
24.0
27.0
31.0
30.0
ns
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
12.0
13.0
15.0
0.0
ns
tCL
Global clock low time
12.0
13.0
15.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
18
21.0
24.0
0.0
ns
tCNT
Global clock minimum clock period
(6)
30.0
35.0
40.0
0.0
ns
fCNT
Maximum internal global clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz
tASU
Array clock input setup time
10.0
10.0
10.0
30.0
ns
tAH
Array clock input hold time
15.0
15.0
15.0
0.0
ns
tACH
Array clock high time
15.0
16.0
17.0
0.0
ns
tACL
Array clock low time
15.0
16.0
17.0
0.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(7)
1.0
1.0
1.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
33.0
38.0
43.0
30.0
ns
tACNT
Array clock minimum clock period
30.0
35.0
40.0
0.0
ns
fACNT
Maximum internal array clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz



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