Altera Corporation

777

EP1810 EPLD

Features

s

High-performance, 48-macrocell Classic EPLD

–

–

Counter frequencies of up to 50 MHz

–

Pipelined data rates of up to 62.5 MHz

s

Programmable I/O architecture with up to 64 inputs or 48 outputs

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Programmable clock option for independent clocking of all registers

s

Macrocells individually programmable as D, T, JK, or SR flipflops, or

for combinatorial operation

s

Available in the following packages (see Figure 15)

–

68-pin ceramic pin-grid array (PGA)

–

68-pin plastic J-lead chip carrier (PLCC)

Figure 15. EP1810 Package Pin-Out Diagrams

Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information.

Windows in ceramic packages only.

68-Pin PGA

L

K

J

H

G

F

E

D

C

B

A

Bottom

View

1

2

3

4

5

6

7

8

9

10 11

EP1810

EP1810

68-Pin PLCC

I/O

I/O

I/O

I/O

INPUT

INPUT

INPUT

CLK1/INPUT

VCC

CLK2/INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

I/O

I/O

I/O

I/O

I/O

INPUT

INPUT

INPUT

CLK4/INPUT

VCC

CLK3/INPUT

INPUT

INPUT

INPUT

I/O

I/O

I/O

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44