EP910 datasheet(4/42 Pages) ALTERA

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Altera Corporation

Classic EPLD Family Data Sheet

The eight product terms of the programmable-AND array feed the 8-input

gate, which then feeds one input to an XOR gate. The other input to the

XOR

gate is connected to a programmable bit that allows the array output

to be inverted. Altera’s MAX+PLUS II software uses the XOR gate to

implement either active-high or active-low logic, or De Morgan’s

inversion to reduce the number of product terms needed to implement a

function.

Programmable Registers

To implement registered functions, each macrocell register can be

individually programmed for D, T, JK, or SR operation. If necessary, the

compilation, the MAX+PLUS II software selects the most efficient register

operation for each registered function to minimize the logic resources

needed by the design. Registers have an individual asynchronous clear

function that is controlled by a dedicated product term. These registers

are cleared automatically during power-up.

In addition, macrocell registers can be individually clocked by either a

global clock or any input or feedback path to the AND array. Altera’s

proprietary programmable I/O architecture allows the designer to

program output and feedback paths for combinatorial or registered

operation in both active-high and active-low modes. These features make

it possible to simultaneously implement a variety of logic functions.

Output Enable/Clock Select

Figure 2 shows the two operating modes (Modes 0 and 1) provided by the

output enable/clock (OE/CLK) select. The OE/CLK select, which is

controlled by a single programmable bit, can be individually configured

for each macrocell. In Mode 0, the tri-state output buffer is controlled by

a single product term. If the output enable is high, the output buffer is

enabled. If the output enable is low, the output has a high-impedance

value. In Mode 0, the macrocell flipflop is clocked by its global clock input

signal.

In Mode 1, the output enable buffer is always enabled, and the macrocell

term. This mode allows registers to be individually clocked by any signal

on the AND array. With both true and complement signals in the AND array,

the register can be configured to trigger on a rising or falling edge. This

product-term-controlled clock configuration also supports gated clock

structures.

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