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CS5571 датащи(PDF) 27 Page - Cirrus Logic

номер детали CS5571
подробное описание детали  짹2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ?誇 ADC
PDF  34 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5571 датащи(HTML) 27 Page - Cirrus Logic

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CS5571
DS768PP1
27
3/25/08
10:56
3.13 Using the CS5571 in Multiplexing Applications
The CS5571 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to
achieve high signal-to-noise performance. This means that once a conversion is started, the converter
takes many samples to compute the resulting output word. The analog input for the signal to be converted
must remain active during the entire conversion until RDY falls.
The CS5571 can be used in multiplexing applications, but the system timing for changing the multiplexer
channel and for starting a new conversion will depend upon the multiplexer system architecture.
The simplest system is illustrated in Figure 27. Any time the multiplexer is changed, the analog signal
presented to the converter must fully settle. After the signal has settled, the CONV signal is issued to the
converter to start a conversion. Being a delta-sigma converter, the signal must remain present at the input
of the converter until the conversion is completed. Once the conversion is completed, RDY falls. At this
time the multiplexer can be changed to the next channel and the data can be read from the serial port.
The CONV signal should be delayed until after the data is read and until the new analog signal has settled.
In this configuration, the throughput of the converter will be dictated by the settling time of the analog input
circuit and the conversion time of the converter. The conversion data can be read from the serial port after
the multiplexer is changed to the new channel while the analog input signal is settling.
Figure 27. Simple Multiplexing Scheme
A more complex multiplexing scheme can be used to increase the throughput of the converter is illustrated
in Figure 28. In this circuit, two banks of multiplexers are used.
Amplifier
Settling Time
Conversion Time
Amplifier
Settling Time
CH1
CH2
CONV
RDY
Advance
Mux
Throughput
CS5571
AIN
ACOM
CH1
CH2
CH3
CH4
90
150pF
2k
4700pF
C0G



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