CS5571

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DS768PP1

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3.11 Serial Port

The serial port on the CS5571 can operate in two different modes: synchronous self clock (SSC) mode &

synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset

and gain registers of the converter are to be read or written. The converter must be idle when reading or

writing to the on-chip registers.

3.11.1 SSC Mode

If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock)

mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is gen-

erated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is

high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the con-

version data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should

be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion

word are output from the port the RDY signal will return to high.

3.11.2 SEC Mode

If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External

Clock mode). In this mode, the user usually monitors RDY. When RDY falls at the end of a conversion,

the conversion data word is placed into the output data register in the serial port. CS is then activated low

to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO

output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data

word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter.

Data bits are advanced on rising edges of SCLK and latched by the subsequent rising edge of SCLK.

If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data

will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port

until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data

at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just

prior to the end of the next conversion and then fall to signal that new data has been written into the serial

port.

3.12 Power Supplies & Grounding

The CS5571 can be configured to operate with its analog supply operating from 5V, or with its analog sup-

plies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or

3.3V.

Figure 6 on page 17 illustrates the device configured to operate from ±2.5V analog. Figure 7 on page 18

illustrates the device configured to operate from 5V analog.

To maximize converter performance, the analog ground and the logic ground for the converter should be

connected at the converter. In the dual analog supply configuration, the analog ground for the ±2.5V sup-

plies should be connected to the VLR pin at the converter with the converter placed entirely over the an-

alog ground plane.

In the single analog supply configuration (+5V), the ground for the +5V supply should be directly tied to

the VLR pin of the converter with the converter placed entirely over the analog ground plane. Refer to

Figure 7 on page 18.