CS5571

8

DS768PP1

3/25/08

10:56

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.

14.

SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down

resistors.

15.

SCLK = MCLK/2.

Parameter

Symbol

Min

Typ

Max

Unit

Serial Port Timing in SSC Mode (SMODE = VL)

Data hold time after SCLK rising

-10

-

ns

Serial Clock (Out)

Pulse Width (low)

(Note 14, 15)

Pulse Width (high)

50

50

-

-

-

-

ns

ns

RDY rising after last SCLK rising

-8

-

MCLKs

CS falling to MSB stable

-10

-

ns

First SCLK rising after CS falling

-8

-

MCLKs

CS hold time (low) after SCLK rising

10

-

-

ns

SCLK, SDO tri-state after CS rising

-5

-

ns

MCLK

RDY

SCLK(o)

SDO

CS

MSB

MSB–1

LSB

LSB+1

Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)