CS2000-OTP

DS758PP1

25

6.3

Global Configuration Parameters

6.3.1

Clock Skip Enable (ClkSkipEn)

This parameter enables clock skipping mode for the PLL and allows the PLL to maintain lock even when

the CLK_IN has missing pulses.

Note:

6.3.2

AUX PLL Lock Output Configuration (AuxLockCfg)

When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this

global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the

polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis-

regarded.

Note:

AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-

fore, the pin polarity is defined relative to the unlock condition.

6.3.3

Reference Clock Input Divider (RefClkDiv[1:0])

Selects the input divider for the timing reference clock.

6.3.4

Enable PLL Clock Output on Unlock (ClkOutUnl)

Defines the state of the PLL output during the PLL unlock condition.

ClkSkipEn

PLL Clock Skipping Mode

0

Disabled.

1

Enabled.

Application:

“CLK_IN Skipping Mode” on page 11

AuxLockCfg

AUX_OUT Driver Configuration

0

Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).

1

Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).

Application:

“Auxiliary Output” on page 19

RefClkDiv[1:0]

Reference Clock Input Divider

REF_CLK Frequency Range

00

÷ 4.

32 MHz to 75 MHz (50 MHz with XTI)

01

÷ 2.

16 MHz to 37.5 MHz

10

÷ 1.

8 MHz to 18.75 MHz

11

Reserved.

Application:

“Internal Timing Reference Clock Divider” on page 10

ClkOutUnl

Clock Output Enable Status

0

Clock outputs are driven ‘low’ when PLL is unlocked.

1

Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).

Application:

“PLL Clock Output” on page 19