PCF8534AUSLASHDASLASH1 datasheet(13/44 Pages) NXP

13 / 44 page

PCF8534A_3

Product data sheet

Rev. 03 — 10 November 2008

13 of 44

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency

fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency

fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr).

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After

power-on, SDA must be HIGH to guarantee that the clock starts.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK becomes the

external clock input. A clock signal must always be applied to the device, removing the

clock can freeze the LCD in a DC state.

7.6 Timing

The timing of the PCF8534A sequences the internal data ﬂow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between all the PCF8534As in the system. The timing also generates the

LCD frame frequency which is derived as an integer division of the clock frequency

(see Table 6). When an external clock is used, the frame frequency is a ﬁxed division of

the internal clock or the frequency applied to pin CLK.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs and one column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data resident in the display register. When less than

60 segment outputs are required the unused segment outputs must be left open-circuit.

Table 6.

LCD frame frequencies

Frame frequency

Nominal frame frequency (Hz)

clk

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