PCF8534AUSLASHDASLASH1 datasheet(21/44 Pages) NXP

21 / 44 page

PCF8534A_3

Product data sheet

Rev. 03 — 10 November 2008

21 of 44

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

8.2 I2C-bus protocol

Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8534A.

The least signiﬁcant bit of the slave address is bit R/W. The PCF8534A is a write-only

device. It will not respond to a read access, so this bit should always be logic 0. The

second bit of the slave address is deﬁned by the level tied at input SA0. Two displays

controlled by PCF8534A can be recognized on the same I2C-bus which allows:

• Up to 16 PCF8534As on the same I2C-bus for very large LCD applications

• The use of two types of LCD multiplex on the same I2C-bus

The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the available PCF8534A

slave addresses. All PCF8534As with the same SA0 level acknowledge in parallel to the

slave address. All PCF8534As with the alternative SA0 level ignore the whole I2C-bus

transfer.

After acknowledgement, the control byte is sent deﬁning if the next byte is RAM or

command information. The control byte also deﬁnes if the next byte is a control byte or

further RAM/command data (see Figure 16 and Table 8). In this way it is possible to

conﬁgure the device and then ﬁll the display RAM with little overhead.

The command bytes and control bytes are also acknowledged by all addressed

PCF8534As connected to the bus.

The display bytes are stored in the display RAM at the address speciﬁed by the data

pointer and the subaddress counter. Both data pointer and subaddress counter are

automatically updated.

The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed

PCF8534A. After the last display byte, the I2C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART I2C-bus access.

Fig 16. Control byte format

Table 8.

Load data pointer command bit description

Bit

Symbol

Value

Description

7CO

continue bit

last control byte

control bytes continue

6RS

command register

data register

5 to 0

not relevant

mgl753

not relevant

210

MSB

LSB

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