PCF8534AUSLASHDASLASH1 datasheet(31/44 Pages) NXP

31 / 44 page

PCF8534A_3

Product data sheet

Rev. 03 — 10 November 2008

31 of 44

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8534As. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by deﬁning a multiplex mode when PCF8534As with

different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the ﬁrst PCF8534A to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF8534A are shown in Figure 22.

Fig 21. Cascaded PCF8534A conﬁguration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

60 segment drives

4 backplanes

60 segment drives

LCD PANEL

PCF8534A

SA0

VSS

VDD

VLCD

VDD

VLCD

001aah619

SDA

SCL

SYNC

CLK

OSC

BP0 to BP3

(open-circuit)

SA0

PCF8534A

BP0 to BP3

2Cb

≤

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