DataOutput

by Transmitter

DataOutput

byReceiver

SCL From

Master

START

Condition

S

1

2

8

9

ClockPulsefor

Acknowledgement

Acknowledge

Not Acknowledge

T0395-01

SCL

SDA

MSB

Slave Address

Acknowledge

Data

Acknowledge

Stop

123456789123456789

T0396-01

S

Slave Address

W

A

Data

A

Data

A

P

FromReceiver

From Transmitter

A =No Acknowledge(SDA High)

A = Acknowledge

S=StartCondition

P =StopCondition

W=Write

R0007-01

TMDS361

During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so

that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the

receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting

device after the last byte is transferred. An example of a write cycle can be found in Figure 40 and Figure 41.

Note that the TMDS361 allows multiple write transfers to occur. See the Example – Writing to the TMDS361

section for more information.

During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its

address. Following this initial acknowledge by the slave, the master device becomes a receiver and

acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from

the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before

it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 42 and Figure 43.

See the Example – Reading from the TMDS361 section for more information.

32

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