TMDS361 datasheet(35/42 Pages) TI

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TMDS361 Read Phase 2

TMDS361

www.ti.com............................................................................................................................................................................................ SLLS919 – DECEMBER 2008

Step 6

I2C stop (master)

Step 6 is optional.

Step 7

I2C start (master)

Step 8

I2C general address (master)

Step 9

I2C acknowledge (slave)

Step 10

I2C read data (slave)

Data

Where data is determined by the logic values contained in the internal registers.

Step 11A

I2C acknowledge (master)

If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.

Step 11B

I2C not acknowledge (master)

Step 12

I2C stop (master)

Table 8. I2C Register 0x01 Lookup Table

BIT

VALUE

STATE

DEFAULT

DESCRIPTION

7:6

Bit 7

Bit 6

Port Select I2C Mode

Port 1 is selected as the active port; HPD on non-selected ports is low. HPD1 can go low, high

or high-Z; there is no external 1-k

Ω pullup resistor to 5 V.

Port 2 is selected as the active port; HPD on non-selected ports is low. HPD2 can go low, high

or high-Z; there is no external 1-k

Ω pullup resistor to 5 V.

Port 3 is selected as the active port; HPD on non-selected ports is low. HPD3 can go low, high

or high-Z; there is no external 1-k

Ω pullup resistor to 5 V.

Standby mode: HPD[1:3] follows HPD_SINK.

5:4

Bit 4

Bit 3

OVS Control

OVS2: DDC sink-side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V

OVS3: DDC sink-side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V

OVS1: DDC sink-side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V

3:2

Bit 3

Bit 2

Output Edge Rate Control

Fastest edge rate + 90 ps

Fastest edge rate + 60 ps

Fastest edge rate + 30 ps

Fastest edge rate

1:0

Bit 1

Bit 0

Power Mode

Device enters low-power mode.

Reserved

Device is in normal-power mode.

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