TMDS361 datasheet(36/42 Pages) TI

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TMDS361

SLLS919 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com

Table 9. I2C Register 0x02 Lookup Table

BIT

VALUE

STATE

DEFAULT

DESCRIPTION

7:6

Bit 7

Bit 6

Port Select Status Indicator

Indicates port 1 is selected as the active port, all other ports are low.

Indicates port 2 is selected as the active port, all other ports are low.

Indicates port 3 is selected as the active port, all other ports are low.

Indicates standby mode: HPD[1:3] follows HPD_SINK.

5:4

Bit 4

Bit 3

OVS Control Status Indicator

Indicates DDC sink side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V

Indicates DDC sink side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V

Indicates DDC sink side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V

3:2

Bit 3

Bit 2

Output edge rate status control

Indicates fastest edge rate + 90 ps

Indicates fastest edge rate + 60 ps

Indicates fastest edge rate + 30 ps

Indicates fastest edge rate

1:0

Bit 1

Bit 0

Power Mode Status Indicator

Indicates device enters low-power mode

Reserved

Indicates device is in normal-power mode

Table 10. I2C Register 0x03 Lookup Table

BIT

VALUE

STATE

DEFAULT

DESCRIPTION

Clock

Clock Detect Circuit Enabled. It is recommended that TMDS361 is used in this default mode

detect

during normal operation where clock detect circuit is enabled . The terminations on the TMDS

enable

input data lines are connected only when valid TMDS clock is detected on the selected port.

Clock

Clock Detect Circuit Disabled. For HDMI compliance testing (TMDS Termination Voltage Test)

detect

clock-detect feature should be disabled. In this mode the terminations on the TMDS input data

disable

lines are always connected when the port is selected.

6:5

RSVD

Reserved

RSVD

Note: Do not write a 1 to this bit

3:0

RSVD

Reserved

Table 11. I2C Register 0x04 Lookup Table

BIT

VALUE

STATE

DEFAULT

DESCRIPTION

Clock

A valid clock signal is detected on the selected port.

detected

No clock

The selected port does not have a valid clock signal.

detect

6:5

RSVD

Reserved

RSVD

This bit should always read 0

3:0

RSVD

Reserved

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