33937 datasheet(13/47 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 8.0 V

≤ VPWR = VSUP ≤ 40 V, -40°C ≤ TA ≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

INTERNAL REGULATORS

VDD Power-Up Time (Until INT High)

8.0 V

≤ VPWR (36)

tPU_VDD

–

2.0

VLS Power-Up Time

16 V

≤ VPWR (37)

tPU_VDD

–

2.0

CHARGE PUMP

Charge Pump Oscillator Frequency

FOSC

125

190

kHz

Charge Pump Slew Rate(38)

SRCP

–

100

–

V/µs

GATE DRIVE

High Side Turn On Time(39)

Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)

tONH

–

High Side Turn On Delay(40)

Delay from Command to 1.0 V, (Figure 7)

tD_ONH

130

265

386

High Side Turn Off Time(39)

Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)

tOFFH

–

High Side Turn Off Delay(40)

Delay from Command to 10 V, (Figure 8)

tD_OFFH

130

265

386

Low Side Turn On Time(39)

Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7)

tONL

–

Low Side Turn On Delay(40)

Delay from Command to 1.0 V, (Figure 7)

tD_ONL

130

265

386

Low Side Turn Off Time(39)

Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8)

tOFFL

–

Low Side Turn Off Delay(40)

Delay from Command to 10 V, (Figure 8)

tD_OFFL

130

265

386

Same Phase Command Delay Match(41)

tD_DIFF

-20

+20

Thermal Filter Duration (42)

tDUR

8.0

–

µs

Notes

36.

The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VDD.

37.

The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and

VLS_CAP. This delay includes the expected time for VDD to rise.

38.

The charge pump operating at 12 V VSYS, 1.0μF pump capacitor, MUR120 diodes and 47 µF filter capacitor.

39.

This parameter is guaranteed by characterization, not production tested.

40.

These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes

one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and

output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision

block. Synchronization time accounts for up to one clock period of variation. See Figure 6.

41.

The maximum separation or overlap of the High and Low Side gate drives, due to propagation delays when commanding one ON and

the other OFF simultaneously, is guaranteed by design.

42.

The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt.

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