33937 datasheet(3/47 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

PIN CONNECTIONS

Figure 3. 33937 Pin Connections

Table 1. 33937 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 22.

Pin Name

Pin Function

Formal Name

Definition

PHASEA

Digital Output

Phase A

Totem Pole output of Phase A comparator. This output is low when the

voltage on PA_HS_S (Source of High Side FET) is less than 50% of VSUP

PGND

Ground

Power Ground

Power ground for charge pump

EN1

Digital Input

Enable 1

Logic signal input must be high (ANDed with EN2) to enable any gate drive

output.

EN2

Digital Input

Enable 2

Logic signal input must be high (ANDed with EN1) to enable any gate drive

output

RST

Digital Input

Reset

Reset input

6, 33, 49,

50, 52, 53

N/C

–

No Connect

Do not connect these pins

PUMP

Power Drive

Out

Pump

Charge pump output

VPUMP

Power Input

Voltage Pump

Charge pump supply

VSUP

Analog Input

Supply Voltage

Supply voltage to the load. This pin is to be connected to the common

Drains of the external High Side FETs

PHASEB

Digital Output

Phase B

Totem Pole output of Phase B comparator. This output is low when the

voltage on PB_HS_S (Source of High Side FET) is less than 50% of VSUP

PHASEC

Digital Output

Phase C

Totem Pole output of Phase C comparator. This output is low when the

voltage on PC_HS_S (Source of High Side FET) is less than 50% of VSUP

.35

PHASEA

PGND

EN1

EN2

RST

N/C

PUMP

VPUMP

VSUP

PHASEB

PHASEC

PA_HS

PA_LS

VDD

PB_HS

PB_LS

INT

SCLK

PC_LS

PC_HS

AMP_OUT

AMP_N

AMP_P

OC_OUT

VPWR

N/C

VLS

N/C

PA_BOOT

PA_HS_G

PA_HS_S

PA_LS_G

PA_LS_S

PB_BOOT

PB_HS_G

PB_HS_S

PB_LS_G

PB_LS_S

PC_BOOT

PC_HS_G

PC_HS_S

PC_LS_G

PC_LS_S

N/C

VLS_CAP

GND1

GND0

VSS

OC_TH

Transparent

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