33937 datasheet(8/47 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 8.0 V

≤ VPWR = VSUP ≤ 40 V, -40°C ≤ TA ≤ 135°C, unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS

VPWR Supply Voltage Startup Threshold(10)

VPWR_ST

–

6.0

8.0

VSUP Supply Current, VPWR = VSUP = 40 V

RST and ENABLE = 5.0 V

No output loads on Gate Drive Pins, No PWM

No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle

ISUP

–

1.0

–

VPWR Supply Current, VPWR = VSUP = 40 V

RST and ENABLE = 5.0 V

No output loads on Gate Drive Pins, No PWM, Outputs initialized

Output Loads = 620 nC per FET, 20 kHz PWM(11)

IPWR_ON

–

Sleep State Supply Current, RST = 0 V

VSUP = 40 V

VPWR = 40 V

ISUP

IPWR

–

100

µA

Sleep State Output Gate Voltage

IG < 100 µA

VGATESS

–

1.3

Trickle Charge Pump (Bootstrap Voltage)

VSUP = 14 V

VBoot

Bootstrap Diode Forward Voltage at 10 mA

–

1.2

VDD INTERNAL REGULATOR

VDD Output Voltage, VPWR = 8 to 40 V, C = 0.47 µF(12)

External Load IDD_EXT = 0 to 1.0 mA

VDD

4.5

–

5.5

Internal VDD Supply Current, VDD = 5.5 V, No External Load

IDD

–

VLS REGULATOR

Peak Output Current, VPWR = 16 V, VLS = 10 V

IPEAK

350

600

800

Linear Regulator Output Voltage, IVLS = 0 to 60 mA(13)

VLS

13.5

VLS Disable Threshold(14)

VTHVLS

7.5

8.0

8.5

Notes

10.

Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. VPWR must exceed this

threshold in order for the Charge Pump and VDD regulator to startup and drive VPWR to > 8.0 V. Once VPWR exceeds 8.0 V, the circuits

will continue to operate even if system voltage drops below 6.0 V.

11.

This parameter is guaranteed by design. It is not production tested.

12.

Minimum external capacitor for stable VDD operation is 0.47 µF.

13.

Recommended external capacitor for the VLS regulator is 2.2 µF low ESR at each pin VLS and VLS_CAP.

14.

When VLS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery is automatic when VLS rises

above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients

on VLS.

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