поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

PSD913F2 датащи(PDF) 77 Page - STMicroelectronics

номер детали PSD913F2
подробное описание детали  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD913F2 датащи(HTML) 77 Page - STMicroelectronics

Back Button PSD913F2 Datasheet HTML 73Page - STMicroelectronics PSD913F2 Datasheet HTML 74Page - STMicroelectronics PSD913F2 Datasheet HTML 75Page - STMicroelectronics PSD913F2 Datasheet HTML 76Page - STMicroelectronics PSD913F2 Datasheet HTML 77Page - STMicroelectronics PSD913F2 Datasheet HTML 78Page - STMicroelectronics PSD913F2 Datasheet HTML 79Page - STMicroelectronics PSD913F2 Datasheet HTML 80Page - STMicroelectronics PSD913F2 Datasheet HTML 81Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 77 / 91 page
background image
PSD9XX Family
PSD935G2
76
-90
-12
Slew
TURBO
Rate
Symbol
Parameter
Conditions
Min
Max
Min
Max
OFF
(Note 1)
Unit
tPD
PLD Input Pin/Feedback to
38
43
Add 20
Sub 6
ns
PLD Combinatorial Output
tARD
PLD Array Delay
23
27
ns
PLD Combinatorial Timing (5 V ± 10%)
NOTE: 1. Fast Slew Rate output available on Port C and F.
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
22
24
tAVLX
Address Setup Time
(Note 1)
7
9
ns
tLXAX
Address Hold Time
(Note 1)
8
10
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
15
18
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
15
18
ns
t DVWH
WR Data Setup Time
(Note 3)
40
45
ns
t WHDX
WR Data Hold Time
(Note 3)
5
8
ns
t WLWH
WR Pulse Width
(Note 3)
40
45
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
8
10
ns
tWHAX2
Trailing Edge of WR to DPLD Address
(Notes 3 and 4)
0
0
ns
Input Invalid
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
33
33
ns
tAVPV
Address Input Valid to Address
(Note 2)
30
35
ns
Output Delay
Write Timing (3.0 V to 3.6 V Versions)
NOTES: 1. Any input used to select an internal PSD935G2 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS signals.
4. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com