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WATCHDOG TIMER

7733 Group User’s Manual

10-10

10.3 Precautions for watchdog timer

1. If dummy data is written to address 6016 when the data length flag (m) is “0,” writing to address 6116 is

simultaneously performed. Accordingly, when a change of the watchdog timer frequency selection flag’s

value (bit 0 at address 6116) is not required, write the same value that is set.

2. In order to stop the watchdog timer in the hold state, the count source which is actually counted by the

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watchdog timer is the logical product of two signals. One is the inverted signal input from pin HOLD, and

the other is a count source which is selected by the watchdog timer frequency selection flag (clock f32

or f512). (Refer to Figure 10.1.1.) Accordingly, there is a possibility that counting is performed when pin

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HOLD’s input signal level changes during a duration which is shorter than 1 cycle of the selected count

source (clock f32 or f512).

Pin HOLD’s input signal level changes

during a duration which is shorter than

1 cycle of clock f32 or f512.

HOLD

pin input signal

Clock f32 or f512

Count source actually

counted by watchdog timer

Fig. 10.3.1 Watchdog timer’s count source

3. When the main clock is not stably supplied, do not use the software reset (that is, writing “1” to the

software reset bit) as a means to reset the microcomputer at a program runaway.

4. When the STP instruction (Refer to chapter “11. STOP AND WAIT MODES”) is executed, the watchdog

timer stops operating. For the system where the watchdog timer is used to detect a program runaway,

select “STP instruction disabled” with “STP instruction option” on “MASK ROM ORDER CONFIRMATION

FORM.”

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