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7733 датащи(PDF) 304 Page - Renesas Technology Corp |
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7733 датащи(HTML) 304 Page - Renesas Technology Corp |
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304 / 940 page ![]() WATCHDOG TIMER 7733 Group User’s Manual 10-7 Table 10.2.2 Watchdog timer’s operation and bit state related to oscillation circuit control Bit state related to oscillation circuit control 10.2 Operation description Port-Xc selection bit (Bit 4 at address 6C16) 0 1 System clock selection bit (Bit 3 at address 6C16) 0 1 0 1 Main clock external input selection bit (Bit 1 at address 6F16) 0 1 0 1 0 1 0 1 Sub clock external input selection bit (Bit 2 at address 6F16) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Watchdog timer’s operation b a b a b a b a b a Note: For each bit’s function, refer to Figures 10.2.1 and 10.2.2. For the procedure of writing to the main clock external input selection bit and the sub clock external input selection bit, refer to Figure 10.2.3. 10.2.3 Operation in wait mode When the system clock stop bit at wait state (bit 5 at address 6C16 ; Refer to Figure 10.2.1.) = “1,” the watchdog timer stops operating in the wait mode. Furthermore, after the wait mode is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. When the system clock stop bit at wait state = “0,” the watchdog timer does not stop. |
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