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WATCHDOG TIMER

7733 Group User’s Manual

10-6

10.2.2 Operation in stop mode

In the stop mode, the watchdog timer stops operating. Immediately after the stop mode is terminated, the

watchdog timer operates as follows.

(1) When stop mode is terminated by a hardware reset

Supply of internal clock

φ starts immediately after the stop mode is terminated, and the microcomputer

performs the “operation after reset.” (Refer to chapter “13. RESET.”) The watchdog timer frequency

selection flag becomes “0,” and the watchdog timer starts counting of the main clockV1 divided by 512

from “FFF16.”

Main clockV1: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”

(2) When stop mode is terminated by an interrupt request generated

According to bit state listed in Table 10.2.2, the watchdog timer operates as “a” or “b” described below.

a. Supply of internal clock

φ starts immediately after the stop mode is terminated, and the routine of

the interrupt which is used to terminate the stop mode is executed. From “FFF16,” the watchdog

timer restarts counting of a count source which was counted just before the STP instruction is

executed (Note 1).

b. Immediately after the stop mode is terminated, the watchdog timer starts counting of a count source

(Note 2) from “FFF16.” Supply of internal clock

φ starts when the watchdog timer’s most significant

bit becomes “0.” (At this time, a watchdog timer interrupt request is not generated.)

When supply of internal clock

φ starts, the microcomputer executes the routine of the interrupt

which is used to terminate the stop mode. From “FFF16,” the watchdog timer restarts counting of

a count source which was counted just before the STP instruction is executed (Note 1).

Notes 1: Clock f32 or f512 is counted.

2: When the system clock selection bit = “0,” clock f32 is counted. When the system clock

selection bit = “1” and the port-Xc selection bit = “0,” clock f8 is counted.

10.2 Operation description

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