SH7265 datasheet(21/2024 Pages) RENESAS

21 / 2024 page

Rev. 1.00 Mar. 14, 2008 Page xxi of xxxvi

16.3.11

Serial Port Register (SCSPTR) ......................................................................... 769

16.3.12

Line Status Register (SCLSR) .......................................................................... 772

16.3.13

Serial Extension Mode Register (SCEMR)....................................................... 773

16.4

Operation .......................................................................................................................... 774

16.4.1

Overview........................................................................................................... 774

16.4.2

Operation in Asynchronous Mode .................................................................... 777

16.4.3

Operation in Clock Synchronous Mode............................................................ 788

16.5

SCIF Interrupts .................................................................................................................796

16.6

Usage Notes ...................................................................................................................... 797

16.6.1

SCFTDR Writing and TDFE Flag .................................................................... 797

16.6.2

SCFRDR Reading and RDF Flag ..................................................................... 797

16.6.3

Restriction on DMAC Usage ............................................................................ 798

16.6.4

Break Detection and Processing ....................................................................... 798

16.6.5

Sending a Break Signal..................................................................................... 798

16.6.6

Receive Data Sampling Timing and Receive Margin

(Asynchronous Mode)....................................................................................... 798

16.6.7

Selection of Base Clock in Asynchronous Mode.............................................. 800

Section 17 Synchronous Serial Communication Unit (SSU) ............................801

17.1

Features............................................................................................................................. 801

17.2

Input/Output Pins.............................................................................................................. 803

17.3

Register Descriptions ........................................................................................................ 804

17.3.1

SS Control Register H (SSCRH) ...................................................................... 805

17.3.2

SS Control Register L (SSCRL) ....................................................................... 807

17.3.3

SS Mode Register (SSMR) ............................................................................... 808

17.3.4

SS Enable Register (SSER) .............................................................................. 809

17.3.5

SS Status Register (SSSR) ................................................................................ 810

17.3.6

SS Control Register 2 (SSCR2) ........................................................................ 814

17.3.7

SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)............................... 815

17.3.8

SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) ................................ 816

17.3.9

SS Shift Register (SSTRSR) ............................................................................. 817

17.4

Operation .......................................................................................................................... 818

17.4.1

Transfer Clock .................................................................................................. 818

17.4.2

Relationship of Clock Phase, Polarity, and Data .............................................. 818

17.4.3

Relationship between Data Input/Output Pins and Shift Register .................... 819

17.4.4

Communication Modes and Pin Functions ....................................................... 821

17.4.5

SSU Mode......................................................................................................... 823

17.4.6

SCS Pin Control and Conflict Error.................................................................. 832

17.4.7

Clock Synchronous Communication Mode ...................................................... 833

17.5

SSU Interrupt Sources and DMAC................................................................................... 840

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